Siemens Digital Industries Software has introduced Tessent Silicon Executable, software that applies semiconductor test patterns directly through high-speed interfaces and protocols, extending its Tessent design-for-test (DFT) workflow into silicon test execution. The software uses test collateral generated by Tessent, applies patterns through a target execution environment and returns results for use in existing debug, diagnosis and analysis flows. The approach is intended to simplify test deployment across automated test equipment (ATE), system-level testing, bench setups and in-system environments. Siemens is launching the software with ATE providers Advantest and Teradyne. Both companies are integrating it into their test platforms to provide a more consistent path from test development to execution. “Semiconductor testing is at an inflection point requiring new scan test delivery methods while minimizing time-to-ramp for a product to release to market. The combination of silicon complexity, multi-die and new transistor technology is driving a growth in test content,” said Ankur Gupta, executive vice president and head of IC, Siemens EDA, Siemens Digital Industries Software. “Tessent Silicon Executable software is embedded in test equipment to directly connect test creation and execution, helping customers apply Tessent-generated patterns consistently and return results to established debug, diagnosis and analysis workflows across test environments. This enables a new level of correlation between environments and provides optimized product economics for device manufacturing” Advantest is integrating the software into its V93000 platform with Link Scale and extending its use to pre-silicon verification and DFT lab engineering through SiConic. “Advantest works with all major EDA vendors to address increasing device complexity and coverage gaps with a seamless workflow across the silicon lifecycle,” said Juergen Serrer, CTO of Advantest. “By integrating Siemens TSE into our V93000 platform with Link Scale and extending it into pre-silicon verification and DFT lab engineering with SiConic, we provide customers with a uniquely consistent path from development to production.” Teradyne is integrating Tessent Silicon Executable into its UltraPort instrument for the UltraFLEXplus tester. The implementation supports scan streaming network (SSN) testing over PCIe, including PCIe Gen 6 interfaces. “In advanced packaging, how test content reaches the device matters as much as the content itself,” said Shannon Poulin, president, Semiconductor Test group, Teradyne. “By integrating Siemens’ Tessent Silicon Executable into our UltraPort instrument for UltraFLEXplus, we are the first tester company to give customers a standard path to run SSN over PCIe for industry-leading PCIe Gen 6 interfaces, which dramatically improves performance and reduces test times.” The post Siemens Extends Tessent Test Flow to Pattern Execution Over PCIe appeared first on EE Times Asia .