Around 2012, key supplier VDL ETG assumed full product responsibility for ASML’s wafer handler. The mission failed. Over the past few years, the curtain has come down on an ambitious ASML-VDL venture that lasted more than a decade. VDL ETG assumed full product responsibility for the wafer handler, a module it was already assembling. Moving development to ETG’s Acht facility in 2012 was supposed to make things simpler and cheaper. In addition to development and production, ASML’s partner would invest in R&D, design, systems engineering, roadmapping and more. VDL ETG was moving up the value chain, taking on a role similar to that of Trumpf and Zeiss. Signing the outsourcing contract kicked off a massive operation. Some 120 engineers, a third of them software developers, temporarily moved from Veldhoven to Acht. Their assignment was to make wafer handler development independent of ASML. That meant setting up the tooling and defining a robust interface between the module and the rest of the machine. Bits&Chips’ Dutch state of semicon 2026 This article is part of the Bits&Chips special edition on the Dutch state of semicon, published on 23 October 2026. Order your hard copy of the special at info@techwatch.nl. One major problem, however, was that “the rest of the machine” consists of many other modules. The wafer handler has to communicate individually with many of them. Throughout all those years, the companies never managed to fully untangle this web of dependencies and define a clean interface. While the engineers in Acht were trying to solve the complex puzzle, the wafer handler’s requirements were also becoming increasingly demanding. By the time ETG started working around 2020 on a version for the 2-nanometer node, intended for the NXE:3800E EUV scanner, it became clear that the assignment was simply too ambitious. ASML and VDL ETG readily acknowledge the failure. “We gave them an impossible assignment,” says Manon Hendriks, Senior Director Sourcing & Procurement at ASML, referring to VDL ETG. “The product we wanted to outsource simply wasn’t outsourceable.” Non-core ASML’s decision to outsource the wafer handler in 2012 followed years of internal debate. The module was a perennial headache. Whenever a wafer handler failed, the consequences were immediately serious: The scanner went down, potentially costing chip manufacturers millions. The module was considered non-core, but it was complex and its software particularly difficult to manage. As the technological demands on lithography intensified around 2010, ASML needed to focus all its attention on EUV and the precision requirements imposed by multi-patterning. The pressure to shed peripheral and non-core activities grew substantially. The wafer handler may not contain core technology, but it’s anything but simple. ASML’s technical department heads in particular were concerned at the time. “The wafer handler was a necessary evil and always ended up getting shortchanged,” recalls an engineer involved from the ETG side. “But ultimately, it’s an incredibly important module because it determines contamination and affects thermal behavior, which in turn affects overlay. Worse still, if it doesn’t work, your machine is down. Fifteen years ago, an hour of downtime could already cost a wafer fab 10 million.” Credit: VDL ETG Hidden roots During the first few years after the transfer, VDL ETG appeared to be making good progress. Things were going well enough that in 2015, the company agreed to an interview with Bits&Chips about the transition. Ultimately, it asked us not to publish the resulting article just yet. The company wanted another six months. After that, however, ETG became more reluctant to discuss the project. In subsequent years, it no longer agreed to provide updates on the wafer handler, although the lingering problems were occasionally mentioned in articles. Going into greater depth was no longer an option. The delay eventually became indefinite. The article we wrote at