Artificial intelligence is reshaping data center architecture by changing where system bottlenecks occur. For years, networking discussions focused primarily on scale-out communication between servers and racks using Ethernet and InfiniBand. Traditional enterprise and cloud applications generated predictable north-south traffic patterns that scaled effectively as long as the external network infrastructure improved. AI workloads have fundamentally changed this model. Modern AI systems rely on accelerator-centric computing, massive model sizes and tightly synchronized execution patterns. As a result, the dominant bottleneck is increasingly found inside the rack rather than between racks. Communication among GPUs, AI accelerators, CPUs and memory devices now determines overall system performance. Historically, CPUs acted as the central processing and communication hub in servers. PCIe was originally designed as an I/O interconnect connecting peripheral devices through CPU root complexes. AI architectures invert this relationship. GPUs and specialized accelerators have become the primary engines of computation, while CPUs mainly orchestrate tasks and manage system operations. The most performance-critical traffic now occurs directly between accelerators and memory resources. This shift creates significant architectural challenges. During AI training, GPUs must continuously synchronize gradients and exchange intermediate data. During inference, accelerators frequently access shared memory pools or communicate with peer accelerators. These interactions are extremely latency-sensitive, and even small communication delays can reduce utilization and overall throughput. One defining characteristic of AI infrastructure is the explosion of east-west traffic within a rack. Large language models (LLMs), recommendation systems, vision transformers, and multimodal AI pipelines all depend on parallelism techniques that require constant synchronization. Data parallelism involves gradient exchanges; model parallelism requires communication between model partitions; and pipeline parallelism depends on rapid activation transfers between stages. As accelerator density increases, local traffic scales dramatically. Racks containing 16, 32 or more GPUs can generate internal bandwidth demands that rival older cluster-wide traffic volumes. In these environments, inside-the-rack connectivity becomes the primary determinant of performance. This trend has driven a broader industry shift toward "scale up before scale out." Instead of deploying many small compute nodes connected through large external networks, AI infrastructure increasingly concentrates compute, memory, and accelerator resources within dense local domains. These tightly coupled systems maximize local bandwidth, reduce latency, and improve accelerator utilization before workloads expand across multiple racks or clusters. The economics also favor this approach. Keeping communication local reduces reliance on expensive external networking equipment, optical links, and power-hungry switching infrastructure. AI racks are evolving into highly integrated super nodes containing GPUs, CPUs, memory pools, SmartNICs, DPUs, and storage devices interconnected through high-bandwidth local fabrics. Traditional server architectures struggle to support these requirements. CPU-centric PCIe topologies were never designed to handle dozens of peer-to-peer accelerator connections with deterministic low latency. When traffic traverses CPU root complexes or non-uniform memory access (NUMA) boundaries, bandwidth becomes fragmented and latency increases. CPUs themselves become chokepoints because their I/O resources are limited and their primary role is orchestration rather than data movement. Static resource allocation is another limitation. Conventional architectures tightly bind devices to individual hosts, making dynamic resource sharing difficult. In modern AI environments where workloads constantly change, th